Cell Library Characterization at Low Voltage Using Non-linear Operating Point Analysis of Local Variations

When CMOS is operated at a supply voltage of 0.5V and below, Random Do pant Fluctuations (RDFs) result in a stochastic component of logic delay that can be comparable to the nominal delay. Moreover, the Probability Density Function (PDF) of this stochastic delay can be highly non-Gaussian. The Non-Linear, Operating Point Analysis of Local Variations (NLOPALV) technique has been shown to be accurate and computationally efficient in simulating any point on the delay PDF of a logic Timing Path (TP). This paper applies the NLOPALV approach to characterizing the stochastic delay of logic cells. NLOPALV theory is presented, and NLOPALV is used to characterize a cell library designed in 28 nm CMOS. NLOPALV is accurate to within 5% compared to SPICE-based Monte Carlo analysis.