{"title":"RFID物流应用中LILLIPUT分组密码的流水线架构","authors":"Pulkit Singh, B. Acharya, R. Chaurasiya","doi":"10.1109/ICCCIS48478.2019.8974530","DOIUrl":null,"url":null,"abstract":"Lightweight cryptography is an exciting field which hits the perfect balance between safety, higher performance, low power consumption, and compactness. Many compact algorithms such as PRESENT, HIGHT, LILLIPUT, KLEIN, KATAN, SFN, and PICCOLO have made the mark in recent years that can be used as lightweight cryptosystems. The reprogrammable devices are highly attractive solutions for encryption algorithm in hardware implementation. A strong focus is placed on high-throughput implementations, which are required to support security for logistics and tracking applications. In this paper, two pipelined architectures are designed for achieving high throughput. Among them, sub-pipelined implementation achieves a high throughput of 684.06 Mbps and 654.20 Mbps on xc5vlx50t-3ff1136 and xc4vlx25-12ff668 devices, respectively. All results are simulated and verified for different devices of Xilinx in Spartan & Virtex families.","PeriodicalId":436154,"journal":{"name":"2019 International Conference on Computing, Communication, and Intelligent Systems (ICCCIS)","volume":"41 6","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Pipelined Architectures of LILLIPUT Block Cipher for RFID Logistic Applications\",\"authors\":\"Pulkit Singh, B. Acharya, R. Chaurasiya\",\"doi\":\"10.1109/ICCCIS48478.2019.8974530\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Lightweight cryptography is an exciting field which hits the perfect balance between safety, higher performance, low power consumption, and compactness. Many compact algorithms such as PRESENT, HIGHT, LILLIPUT, KLEIN, KATAN, SFN, and PICCOLO have made the mark in recent years that can be used as lightweight cryptosystems. The reprogrammable devices are highly attractive solutions for encryption algorithm in hardware implementation. A strong focus is placed on high-throughput implementations, which are required to support security for logistics and tracking applications. In this paper, two pipelined architectures are designed for achieving high throughput. Among them, sub-pipelined implementation achieves a high throughput of 684.06 Mbps and 654.20 Mbps on xc5vlx50t-3ff1136 and xc4vlx25-12ff668 devices, respectively. All results are simulated and verified for different devices of Xilinx in Spartan & Virtex families.\",\"PeriodicalId\":436154,\"journal\":{\"name\":\"2019 International Conference on Computing, Communication, and Intelligent Systems (ICCCIS)\",\"volume\":\"41 6\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 International Conference on Computing, Communication, and Intelligent Systems (ICCCIS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCCIS48478.2019.8974530\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International Conference on Computing, Communication, and Intelligent Systems (ICCCIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCCIS48478.2019.8974530","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Pipelined Architectures of LILLIPUT Block Cipher for RFID Logistic Applications
Lightweight cryptography is an exciting field which hits the perfect balance between safety, higher performance, low power consumption, and compactness. Many compact algorithms such as PRESENT, HIGHT, LILLIPUT, KLEIN, KATAN, SFN, and PICCOLO have made the mark in recent years that can be used as lightweight cryptosystems. The reprogrammable devices are highly attractive solutions for encryption algorithm in hardware implementation. A strong focus is placed on high-throughput implementations, which are required to support security for logistics and tracking applications. In this paper, two pipelined architectures are designed for achieving high throughput. Among them, sub-pipelined implementation achieves a high throughput of 684.06 Mbps and 654.20 Mbps on xc5vlx50t-3ff1136 and xc4vlx25-12ff668 devices, respectively. All results are simulated and verified for different devices of Xilinx in Spartan & Virtex families.