{"title":"基于65nm CMOS的3位20gs /s ADC设计","authors":"D. Ferenci, M. Grozing, M. Berroth","doi":"10.1109/RME.2009.5201305","DOIUrl":null,"url":null,"abstract":"A 20 GS/s 3 bit flash ADC with an analog input bandwidth of 10 GHz is realized in a 65nm LP CMOS technology. By employing a fourfold parallelization a high sample rate is achieved, while a large input bandwidth is maintained. Simulations at 20 GS/s exhibit an effective resolution of 2.5 Bits at the Nyquist frequency. The chip area is 5.2mm2 while the ADC core area is 0.16mm2.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"50 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Design of a 3 Bit 20 GS/s ADC in 65 nm CMOS\",\"authors\":\"D. Ferenci, M. Grozing, M. Berroth\",\"doi\":\"10.1109/RME.2009.5201305\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 20 GS/s 3 bit flash ADC with an analog input bandwidth of 10 GHz is realized in a 65nm LP CMOS technology. By employing a fourfold parallelization a high sample rate is achieved, while a large input bandwidth is maintained. Simulations at 20 GS/s exhibit an effective resolution of 2.5 Bits at the Nyquist frequency. The chip area is 5.2mm2 while the ADC core area is 0.16mm2.\",\"PeriodicalId\":245992,\"journal\":{\"name\":\"2009 Ph.D. Research in Microelectronics and Electronics\",\"volume\":\"50 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-07-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 Ph.D. Research in Microelectronics and Electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RME.2009.5201305\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Ph.D. Research in Microelectronics and Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RME.2009.5201305","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 20 GS/s 3 bit flash ADC with an analog input bandwidth of 10 GHz is realized in a 65nm LP CMOS technology. By employing a fourfold parallelization a high sample rate is achieved, while a large input bandwidth is maintained. Simulations at 20 GS/s exhibit an effective resolution of 2.5 Bits at the Nyquist frequency. The chip area is 5.2mm2 while the ADC core area is 0.16mm2.
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