二维离散小波变换的可伸缩收缩阵列结构

VLSI Signal Processing, VIII Pub Date : 1995-10-16 DOI:10.1109/VLSISP.1995.527501

J. Chen, M. Bayoumi

{"title":"二维离散小波变换的可伸缩收缩阵列结构","authors":"J. Chen, M. Bayoumi","doi":"10.1109/VLSISP.1995.527501","DOIUrl":null,"url":null,"abstract":"A systematic synthesis approach has been developed for scalable systolic array architecture for a 2D discrete wavelet transform (DWT) based on the data dependence analysis and linear index space transformation. The proposed architecture has regular topology, local routing, simple controller and high throughput rate. It can be easily extended to different parameters of various levels, macroblocks and filters. The derived architecture has been prototyped using Cadence Edge Framework.","PeriodicalId":286121,"journal":{"name":"VLSI Signal Processing, VIII","volume":"266 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"21","resultStr":"{\"title\":\"A scalable systolic array architecture for 2D discrete wavelet transforms\",\"authors\":\"J. Chen, M. Bayoumi\",\"doi\":\"10.1109/VLSISP.1995.527501\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A systematic synthesis approach has been developed for scalable systolic array architecture for a 2D discrete wavelet transform (DWT) based on the data dependence analysis and linear index space transformation. The proposed architecture has regular topology, local routing, simple controller and high throughput rate. It can be easily extended to different parameters of various levels, macroblocks and filters. The derived architecture has been prototyped using Cadence Edge Framework.\",\"PeriodicalId\":286121,\"journal\":{\"name\":\"VLSI Signal Processing, VIII\",\"volume\":\"266 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-10-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"21\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"VLSI Signal Processing, VIII\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSISP.1995.527501\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"VLSI Signal Processing, VIII","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSISP.1995.527501","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 21

摘要

提出了一种基于数据相关性分析和线性索引空间变换的二维离散小波变换可伸缩收缩阵列结构的系统综合方法。该架构具有拓扑规则、本地路由、控制器简单、吞吐量高的特点。它可以很容易地扩展到各种级别，宏块和过滤器的不同参数。衍生的架构已经使用Cadence边缘框架原型。

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A scalable systolic array architecture for 2D discrete wavelet transforms

A systematic synthesis approach has been developed for scalable systolic array architecture for a 2D discrete wavelet transform (DWT) based on the data dependence analysis and linear index space transformation. The proposed architecture has regular topology, local routing, simple controller and high throughput rate. It can be easily extended to different parameters of various levels, macroblocks and filters. The derived architecture has been prototyped using Cadence Edge Framework.

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来源期刊

VLSI Signal Processing, VIII

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