三个版本的数字硬件实现了一个多层感知器在0.7 /spl mu/ cmos的设计

1996 Fourth IEEE International Workshop on Cellular Neural Networks and their Applications Proceedings (CNNA-96) Pub Date : 1996-06-24 DOI:10.1109/CNNA.1996.566607

V. Tryba, B. Kiziloglu

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引用次数: 0

摘要

本文介绍了多层感知器作为神经专用集成电路的三个实现版本。一个有9个神经元的完全并行版本是快速版本，一个在神经元内部进行顺序处理的版本，一个有一个多路复用的快速神经元的版本。这三个版本在大小和速度上进行了比较。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Three versions of a digital hardware implementation of a multi-layer perceptron in 0.7 /spl mu/ CMOS-design

In this paper, three versions of an implementation of a multi-layer perceptron as a neural ASIC are presented. A fully parallel version with 9 neurons as a fast version, a version with sequential processing inside the neurons, and a version with one fast neuron which is multiplexed. The three versions are compared in size and speed.

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1996 Fourth IEEE International Workshop on Cellular Neural Networks and their Applications Proceedings (CNNA-96)

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