Design of an energy-efficient turbo decoder for 3/sup RD/ generation wireless applications

A rate-1/3 8-state log-MAP turbo decoder architecture for third-generation wireless data terminals is designed. Several architectural and logic level techniques are applied throughout the design to reduce area, power, and increase throughout of the turbo decoder. The decoder is described in VHDL and synthesized into a 0.18 /spl mu/ 6-metal CMOS standard cell library. The synthesized decoder has a core area of about 0.54 mm/sup 2/. At 100 MHz clock frequency, the decoder achieves a data rate of 5 Mb/s using 5 iterations and produces power consumption of about 376 mW; that amounts to an energy consumption of about 15 nJ/b/iteration.