{"title":"面积高效和高吞吐量的CAVLC编码器,适用于1920×1080@30p H.264/AVC","authors":"Changsu Han, Jae Hun Lee","doi":"10.1109/ICCE.2009.5012195","DOIUrl":null,"url":null,"abstract":"This paper proposes a high performance hardware architecture design for the H.264/AVC CAVLC encoder. The proposed architecture can make a realtime process for 1920×1080 @ 30p. With the synthesis constraint of a 114MHz clock, the hardware cost of the proposed design is 7389 gates based on SS65LP 65nm technology.","PeriodicalId":154986,"journal":{"name":"2009 Digest of Technical Papers International Conference on Consumer Electronics","volume":"221 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Area efficient and high throughput CAVLC encoder for 1920×1080@30p H.264/AVC\",\"authors\":\"Changsu Han, Jae Hun Lee\",\"doi\":\"10.1109/ICCE.2009.5012195\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a high performance hardware architecture design for the H.264/AVC CAVLC encoder. The proposed architecture can make a realtime process for 1920×1080 @ 30p. With the synthesis constraint of a 114MHz clock, the hardware cost of the proposed design is 7389 gates based on SS65LP 65nm technology.\",\"PeriodicalId\":154986,\"journal\":{\"name\":\"2009 Digest of Technical Papers International Conference on Consumer Electronics\",\"volume\":\"221 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-05-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 Digest of Technical Papers International Conference on Consumer Electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCE.2009.5012195\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Digest of Technical Papers International Conference on Consumer Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCE.2009.5012195","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Area efficient and high throughput CAVLC encoder for 1920×1080@30p H.264/AVC
This paper proposes a high performance hardware architecture design for the H.264/AVC CAVLC encoder. The proposed architecture can make a realtime process for 1920×1080 @ 30p. With the synthesis constraint of a 114MHz clock, the hardware cost of the proposed design is 7389 gates based on SS65LP 65nm technology.