音频应用中可变过采样率σ - δ模数转换器的18位抽取器设计

2014 International Conference on Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment and Management (HNICEM) Pub Date : 2014-11-01 DOI:10.1109/HNICEM.2014.7016227

O. J. Gerasta, Harrez Villaruz, Dominic O. Cagadas

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引用次数: 0

摘要

基于台积电0.13 um CMOS技术，成功实现了一种用于音频应用的可变过采样率σ - δ模数转换器的18位抽取器设计。本课题的行为模型采用MATLAB实现，实际实现采用RTL Code，并借助于Verilog Compiler Simulator。该十进制数设计中使用的过采样率为32、64、128和256。此外，该抽取器使用1个sinc滤波器和2个半带滤波器作为整个系统的主要模块。与行为模拟结果相比，设计的结果实际上使信号的延迟最小化。总单元面积减少，达到理想的信噪比。

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Design of 18-bit decimator for sigma-delta analog to digital converter with variable oversampling rate for audio application

An 18-bit decimator design for sigma-delta analog to digital converter with variable oversampling rate for audio application was successfully implemented in TSMC 0.13 um Logic CMOS Technology. Behavioral model of this project is implemented using MATLAB and actual implementation using RTL Code with the aid of Verilog Compiler Simulator. The oversampling rates used in this decimator design are 32, 64, 128 and 256. Also, this decimator uses 1 sinc filter and 2 halfband filters as the main blocks for the whole system. The result of the design actually minimized the delay of the signal as compared to the behavioral simulation obtained. The total cell area is reduced reaching the desirable signal-to-noise ratio.

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2014 International Conference on Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment and Management (HNICEM)

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