基于电压反射理论的dv/dt滤波器设计新方法

Bernard Arhin, H. Cha
{"title":"基于电压反射理论的dv/dt滤波器设计新方法","authors":"Bernard Arhin, H. Cha","doi":"10.1109/gpecom55404.2022.9815657","DOIUrl":null,"url":null,"abstract":"This paper proposes a dv/dt suppression second-order RLC filter for an inverter-cable-high impedance load system. The dv/dt filter placed at the inverter output is designed purposely to minimize excessive voltage overshoot at the load terminal by reducing dv/dt or voltage pulse rise time. A 500 V unit pulse of inverter source is connected over several cable lengths to a high impedance load with a load reflection coefficient of 0.9. Voltage overshoot in terms of the ratio of rise time to propagation time is analyzed and verified by Matlab/Simulink environment. In addition, a new design method for the second-order dv/dt filter is proposed. From the simulation results, the dv/dt filter is able to reduce a high load peak voltage of approximately 950 V to 588.6 V in a 50m inverter-cable-load system, and increase to 1 µs of rise time at the load terminal.","PeriodicalId":441321,"journal":{"name":"2022 4th Global Power, Energy and Communication Conference (GPECOM)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A New dv/dt Filter Design Method using the Voltage Reflection Theory\",\"authors\":\"Bernard Arhin, H. Cha\",\"doi\":\"10.1109/gpecom55404.2022.9815657\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a dv/dt suppression second-order RLC filter for an inverter-cable-high impedance load system. The dv/dt filter placed at the inverter output is designed purposely to minimize excessive voltage overshoot at the load terminal by reducing dv/dt or voltage pulse rise time. A 500 V unit pulse of inverter source is connected over several cable lengths to a high impedance load with a load reflection coefficient of 0.9. Voltage overshoot in terms of the ratio of rise time to propagation time is analyzed and verified by Matlab/Simulink environment. In addition, a new design method for the second-order dv/dt filter is proposed. From the simulation results, the dv/dt filter is able to reduce a high load peak voltage of approximately 950 V to 588.6 V in a 50m inverter-cable-load system, and increase to 1 µs of rise time at the load terminal.\",\"PeriodicalId\":441321,\"journal\":{\"name\":\"2022 4th Global Power, Energy and Communication Conference (GPECOM)\",\"volume\":\"88 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 4th Global Power, Energy and Communication Conference (GPECOM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/gpecom55404.2022.9815657\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 4th Global Power, Energy and Communication Conference (GPECOM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/gpecom55404.2022.9815657","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

本文提出了一种用于逆变器-电缆-高阻抗负载系统的dv/dt抑制二阶RLC滤波器。放置在逆变器输出端的dv/dt滤波器旨在通过减少dv/dt或电压脉冲上升时间来最小化负载端的过电压超调。逆变器源的500 V单位脉冲通过几根电缆长度连接到负载反射系数为0.9的高阻抗负载。通过Matlab/Simulink环境对电压超调的上升时间与传播时间之比进行了分析和验证。此外,还提出了一种二阶dv/dt滤波器的新设计方法。仿真结果表明,在50m逆变器-电缆负载系统中,dv/dt滤波器能够将约950 V的高负载峰值电压降低到588.6 V,并在负载端增加1µs的上升时间。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A New dv/dt Filter Design Method using the Voltage Reflection Theory
This paper proposes a dv/dt suppression second-order RLC filter for an inverter-cable-high impedance load system. The dv/dt filter placed at the inverter output is designed purposely to minimize excessive voltage overshoot at the load terminal by reducing dv/dt or voltage pulse rise time. A 500 V unit pulse of inverter source is connected over several cable lengths to a high impedance load with a load reflection coefficient of 0.9. Voltage overshoot in terms of the ratio of rise time to propagation time is analyzed and verified by Matlab/Simulink environment. In addition, a new design method for the second-order dv/dt filter is proposed. From the simulation results, the dv/dt filter is able to reduce a high load peak voltage of approximately 950 V to 588.6 V in a 50m inverter-cable-load system, and increase to 1 µs of rise time at the load terminal.
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