Soon-Moon Jung, H. Lim, W. Cho, Hoosung Cho, H. Hong, Jaehun Jeong, Sugwoo Jung, H. Park, Byoungkeun Son, Y. Jang, Kinam Kim
{"title":"软误差免疫0.46 /spl mu/m/sup 2/ SRAM单元，采用65纳米CMOS技术，用于超高速SRAM","authors":"Soon-Moon Jung, H. Lim, W. Cho, Hoosung Cho, H. Hong, Jaehun Jeong, Sugwoo Jung, H. Park, Byoungkeun Son, Y. Jang, Kinam Kim","doi":"10.1109/IEDM.2003.1269281","DOIUrl":null,"url":null,"abstract":"The smallest SRAM cell, 0.46 um/sup 2/, is realized by a single pitch cell layout, gate poly trim mask technique, 80 nm contact holes formed by polymer attaching process, and a 193 nm ArF lithography process. The MIM (metal-insulator-metal) node capacitor is developed and used for the first time in the SRAM cell to reduce the radiation induced soft error rate, dramatically. The high performance transistors are developed with a channel length of 70 nm, plasma nitrided 13 /spl Aring/ gate oxide, low thermal budget sidewall spacer, and CoSix.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"172 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Soft error immune 0.46 /spl mu/m/sup 2/ SRAM cell with MIM node capacitor by 65 nm CMOS technology for ultra high speed SRAM\",\"authors\":\"Soon-Moon Jung, H. Lim, W. Cho, Hoosung Cho, H. Hong, Jaehun Jeong, Sugwoo Jung, H. Park, Byoungkeun Son, Y. Jang, Kinam Kim\",\"doi\":\"10.1109/IEDM.2003.1269281\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The smallest SRAM cell, 0.46 um/sup 2/, is realized by a single pitch cell layout, gate poly trim mask technique, 80 nm contact holes formed by polymer attaching process, and a 193 nm ArF lithography process. The MIM (metal-insulator-metal) node capacitor is developed and used for the first time in the SRAM cell to reduce the radiation induced soft error rate, dramatically. The high performance transistors are developed with a channel length of 70 nm, plasma nitrided 13 /spl Aring/ gate oxide, low thermal budget sidewall spacer, and CoSix.\",\"PeriodicalId\":344286,\"journal\":{\"name\":\"IEEE International Electron Devices Meeting 2003\",\"volume\":\"172 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-12-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Electron Devices Meeting 2003\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2003.1269281\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Electron Devices Meeting 2003","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2003.1269281","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Soft error immune 0.46 /spl mu/m/sup 2/ SRAM cell with MIM node capacitor by 65 nm CMOS technology for ultra high speed SRAM
The smallest SRAM cell, 0.46 um/sup 2/, is realized by a single pitch cell layout, gate poly trim mask technique, 80 nm contact holes formed by polymer attaching process, and a 193 nm ArF lithography process. The MIM (metal-insulator-metal) node capacitor is developed and used for the first time in the SRAM cell to reduce the radiation induced soft error rate, dramatically. The high performance transistors are developed with a channel length of 70 nm, plasma nitrided 13 /spl Aring/ gate oxide, low thermal budget sidewall spacer, and CoSix.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
