{"title":"兼容USB 2.0应用的耐高压I/O电路设计","authors":"Moon-Jung Kim, Henrik Icking, H. Gossner, T. Lee","doi":"10.1109/CICC.2007.4405779","DOIUrl":null,"url":null,"abstract":"We present design strategies of high-voltage tolerant I/O circuits for interfaces of 3.3 V or higher. The test vehicle is a USB 2.0-compliant I/O circuit. This is a challenging example because USB 2.0 requires substantial over-voltage tolerance from -IV to 5.25 V. In addition, USB 2.0 requires continuous monitoring of this condition and protection when no power is present. The proposed concept is demonstrated in a 90 nm CMOS process.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"High-Voltage-Tolerant I/O Circuit Design for USB 2.0-Compliant Applications\",\"authors\":\"Moon-Jung Kim, Henrik Icking, H. Gossner, T. Lee\",\"doi\":\"10.1109/CICC.2007.4405779\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present design strategies of high-voltage tolerant I/O circuits for interfaces of 3.3 V or higher. The test vehicle is a USB 2.0-compliant I/O circuit. This is a challenging example because USB 2.0 requires substantial over-voltage tolerance from -IV to 5.25 V. In addition, USB 2.0 requires continuous monitoring of this condition and protection when no power is present. The proposed concept is demonstrated in a 90 nm CMOS process.\",\"PeriodicalId\":130106,\"journal\":{\"name\":\"2007 IEEE Custom Integrated Circuits Conference\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2007.4405779\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2007.4405779","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High-Voltage-Tolerant I/O Circuit Design for USB 2.0-Compliant Applications
We present design strategies of high-voltage tolerant I/O circuits for interfaces of 3.3 V or higher. The test vehicle is a USB 2.0-compliant I/O circuit. This is a challenging example because USB 2.0 requires substantial over-voltage tolerance from -IV to 5.25 V. In addition, USB 2.0 requires continuous monitoring of this condition and protection when no power is present. The proposed concept is demonstrated in a 90 nm CMOS process.
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