A 0.5-to-3 GHz software-defined radio receiver using sample domain signal processing

A 0.5-to-3 GHz software-defined radio receiver leveraging Sampled Domain Signal Processing (SPSD) is demonstrated in a 65nm LP CMOS technology. The SDSP approach achieves band-pass filtering, harmonic rejection, and frequency translation simultaneously. Input impedance matching is achieved in an active translational loop that tracks the desired RF frequency. The chip includes a wideband frequency synthesizer, multi-phase nonoverlapping clock generation circuitry, bandgap and power supply regulators. It achieves out-of-band IIP3 > 11.7 dBm, IIP2 > 58 dBm, NF = 5.5 ~ 8.8 dB, and uncalibrated 3rd and 5th order harmonic rejections exceeding 47 dB and 52 dB, respectively.