P. Diodato, J. Clemens, W. Troutman, W. S. Lindenberger
{"title":"一种可重复使用的嵌入式DRAM宏单元","authors":"P. Diodato, J. Clemens, W. Troutman, W. S. Lindenberger","doi":"10.1109/CICC.1997.606642","DOIUrl":null,"url":null,"abstract":"A charged based analysis is used to compare three DRAM cells embedded in a 0.25 /spl mu/m ASIC environment. Critical charge, bit-line response, and sense amplifier sensitivity are calculated. Wafer probe measurements are shown that demonstrate milli-second hold times and explanations presented in support of using multi-transistor DRAM cells for the vast majority of high performance embedded ASIC applications.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"141 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A reusable embedded DRAM macrocell\",\"authors\":\"P. Diodato, J. Clemens, W. Troutman, W. S. Lindenberger\",\"doi\":\"10.1109/CICC.1997.606642\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A charged based analysis is used to compare three DRAM cells embedded in a 0.25 /spl mu/m ASIC environment. Critical charge, bit-line response, and sense amplifier sensitivity are calculated. Wafer probe measurements are shown that demonstrate milli-second hold times and explanations presented in support of using multi-transistor DRAM cells for the vast majority of high performance embedded ASIC applications.\",\"PeriodicalId\":111737,\"journal\":{\"name\":\"Proceedings of CICC 97 - Custom Integrated Circuits Conference\",\"volume\":\"141 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-05-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of CICC 97 - Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.1997.606642\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1997.606642","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A charged based analysis is used to compare three DRAM cells embedded in a 0.25 /spl mu/m ASIC environment. Critical charge, bit-line response, and sense amplifier sensitivity are calculated. Wafer probe measurements are shown that demonstrate milli-second hold times and explanations presented in support of using multi-transistor DRAM cells for the vast majority of high performance embedded ASIC applications.
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