在线测试fpga的逻辑单元设计

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI:10.1109/APASIC.1999.824101

P. Lala, A. Singh

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引用次数: 1

摘要

本文提出了一种自检逻辑单元，可作为在线测试fpga的构建模块。所提出的单元由三个4对1多路复用器、一个2对1多路复用器和一个D触发器组成。这些多路复用器和D触发器采用差分级联码电压开关逻辑设计。任何单晶体管故障(卡通/关断)以及多路复用器或D触发器输入端的单卡通故障都可以在线检测。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Logic cell design for on-line testable FPGAs

This paper proposes a self-checking logic cell that can be used as the building block for on-line testable FPGAs. The proposed cell consists of three 4-to-1 multiplexers, a 2-to-1 multiplexers and a D flip-flop. These multiplexers and the D flip-flop are designed using differential cascode voltage switch logic. Any single transistor fault (stuck-on/off) as well as single stuck-at faults at the inputs of the multiplexers or the D flip-flop can be detected on-line.

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AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)

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