{"title":"现场可编程混合信号系统的模数分划","authors":"S. Ganesan, R. Vemuri","doi":"10.1109/ARVLSI.2001.915559","DOIUrl":null,"url":null,"abstract":"Synthesis of mixed-signal designs from behavioral specifications must address analog-digital partitioning. In other words, determining what portions of the design are best implemented using analog and digital circuitry. In this work, we target reconfigurable mixed-signal systems composed of field-programmable analog and digital arrays. These field-programmable systems are invaluable for rapid hardware prototyping and evaluation. We begin with system behavior specified using a signal-/data-flow graph representation. This is partitioned into analog and digital domains, and then mapped onto the target mixed-signal hardware. The solution must satisfy constraints imposed by the target mixed-signal architecture on available configurable resources, available data converters, their resolution and speed, and I/O pins. The quality of the solution is evaluated based two metrics, namely feasibility and performance cost. The former is a measure of the validity of the solution with respect to the constraints. The latter measures the performance of the system based on area, bandwidth and noise.","PeriodicalId":424368,"journal":{"name":"Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Analog-digital partitioning for field-programmable mixed signal systems\",\"authors\":\"S. Ganesan, R. Vemuri\",\"doi\":\"10.1109/ARVLSI.2001.915559\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Synthesis of mixed-signal designs from behavioral specifications must address analog-digital partitioning. In other words, determining what portions of the design are best implemented using analog and digital circuitry. In this work, we target reconfigurable mixed-signal systems composed of field-programmable analog and digital arrays. These field-programmable systems are invaluable for rapid hardware prototyping and evaluation. We begin with system behavior specified using a signal-/data-flow graph representation. This is partitioned into analog and digital domains, and then mapped onto the target mixed-signal hardware. The solution must satisfy constraints imposed by the target mixed-signal architecture on available configurable resources, available data converters, their resolution and speed, and I/O pins. The quality of the solution is evaluated based two metrics, namely feasibility and performance cost. The former is a measure of the validity of the solution with respect to the constraints. The latter measures the performance of the system based on area, bandwidth and noise.\",\"PeriodicalId\":424368,\"journal\":{\"name\":\"Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-03-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ARVLSI.2001.915559\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARVLSI.2001.915559","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Analog-digital partitioning for field-programmable mixed signal systems
Synthesis of mixed-signal designs from behavioral specifications must address analog-digital partitioning. In other words, determining what portions of the design are best implemented using analog and digital circuitry. In this work, we target reconfigurable mixed-signal systems composed of field-programmable analog and digital arrays. These field-programmable systems are invaluable for rapid hardware prototyping and evaluation. We begin with system behavior specified using a signal-/data-flow graph representation. This is partitioned into analog and digital domains, and then mapped onto the target mixed-signal hardware. The solution must satisfy constraints imposed by the target mixed-signal architecture on available configurable resources, available data converters, their resolution and speed, and I/O pins. The quality of the solution is evaluated based two metrics, namely feasibility and performance cost. The former is a measure of the validity of the solution with respect to the constraints. The latter measures the performance of the system based on area, bandwidth and noise.