侧壁沉积与反蚀技术在纳米级器件集成中的应用

U. Hilleringmann, F. Vidor, F. Assion
{"title":"侧壁沉积与反蚀技术在纳米级器件集成中的应用","authors":"U. Hilleringmann, F. Vidor, F. Assion","doi":"10.1109/SCAT.2014.7055128","DOIUrl":null,"url":null,"abstract":"The side-wall deposition and etch-back technology is a simple method to produce nanometer scale lines and trenches or gaps. It can be used in semiconductor technology for electronic device integration. This paper reflects its application for field effect transistors in bulk silicon and demonstrates its potential for nanometer scale particle transistor integration. Silicon and ZnO nanoparticle field effect transistors using different setup structures show on/off ratios of up to 4500 and mobilities of some cm2V·1s-1. Although the best structures apply high temperature processing, a reduced temperature process for ZnO nanoparticle transistor integration on glass and foil substrates is presented.","PeriodicalId":315622,"journal":{"name":"Proceedings of the 2nd Pan African International Conference on Science, Computing and Telecommunications (PACT 2014)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Application of side-wall deposition and etch-back technology for nanometer scale device integration\",\"authors\":\"U. Hilleringmann, F. Vidor, F. Assion\",\"doi\":\"10.1109/SCAT.2014.7055128\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The side-wall deposition and etch-back technology is a simple method to produce nanometer scale lines and trenches or gaps. It can be used in semiconductor technology for electronic device integration. This paper reflects its application for field effect transistors in bulk silicon and demonstrates its potential for nanometer scale particle transistor integration. Silicon and ZnO nanoparticle field effect transistors using different setup structures show on/off ratios of up to 4500 and mobilities of some cm2V·1s-1. Although the best structures apply high temperature processing, a reduced temperature process for ZnO nanoparticle transistor integration on glass and foil substrates is presented.\",\"PeriodicalId\":315622,\"journal\":{\"name\":\"Proceedings of the 2nd Pan African International Conference on Science, Computing and Telecommunications (PACT 2014)\",\"volume\":\"81 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-07-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2nd Pan African International Conference on Science, Computing and Telecommunications (PACT 2014)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SCAT.2014.7055128\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2nd Pan African International Conference on Science, Computing and Telecommunications (PACT 2014)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SCAT.2014.7055128","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

侧壁沉积和反蚀刻技术是一种制造纳米尺度线和沟槽或缝隙的简单方法。它可用于半导体技术中的电子器件集成。本文反映了它在体硅场效应晶体管中的应用,并论证了它在纳米级粒子晶体管集成方面的潜力。采用不同设置结构的硅和ZnO纳米粒子场效应晶体管的开/关比可达4500,迁移率可达cm2V·1s-1。虽然最好的结构采用高温加工,但提出了一种在玻璃和箔基板上集成氧化锌纳米粒子晶体管的低温工艺。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Application of side-wall deposition and etch-back technology for nanometer scale device integration
The side-wall deposition and etch-back technology is a simple method to produce nanometer scale lines and trenches or gaps. It can be used in semiconductor technology for electronic device integration. This paper reflects its application for field effect transistors in bulk silicon and demonstrates its potential for nanometer scale particle transistor integration. Silicon and ZnO nanoparticle field effect transistors using different setup structures show on/off ratios of up to 4500 and mobilities of some cm2V·1s-1. Although the best structures apply high temperature processing, a reduced temperature process for ZnO nanoparticle transistor integration on glass and foil substrates is presented.
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