An all-digital clock generator for dynamic frequency scaling

An all-digital clock generator for dynamic frequency scaling is presented by using a cyclic clock multiplier. It realizes the fractional or multiplied output clock within four reference clock cycles. The frequency of the output clock can be programmed as Mfref/N (fref is the reference clock frequency, 1≦M≦7, and 1≦N≦8). It has been fabricated in a 0.18um CMOS process. The measured rms jitter of the output clock is 3ps when the input clock is 133MHz, M is 7, and N is 1 and consumes 53mW from a supply of 1.8V. The core area of this clock generator is 0.26mm2.