Simulating and Evaluating a Quaternary Logic FPGA Based on Floating-gate Memories and Voltage Division

Technology scaling cannot meet consumer demands, especially for binary circuits. Previous studies proposed addressing this with multi-valued logic (MVL) architectures, but these architectures use non-standard fabrication techniques and optimistic performance analysis. This study presents a new quaternary FPGA (QFPGA) architecture based on floating-gate memories that standard CMOS fabrication can fabricate: programming floating-gates implement a voltage divider, and these divided voltages represent one of four distinct logic values. When simulated with open-source FinFET SPICE models, the proposed architecture obtains competitive delay and power performance compared to equivalent binary and QFPGA architectures from literature. Results show the proposed QFPGA basic logic element (BLE) requires half the area and dissipates a third of the power density compared to QFPGA architectures from literature. When projecting BLE performance onto benchmark circuits, implementing circuits requires up to 55% less area and one-third the power, and the proposed architecture can operate at clock speeds up to three times faster than binary equivalents. Future studies will investigate accurate modeling of interconnects to better account for their performance impacts and will explore efficient architectures for programming MVL memories when they're used in FPGAs.