Low-power analog fuzzy rule implementation based on a linear MOS transistor network

An analog fuzzy rule circuit is proposed, which is based on a network of MOS transistors exploited as linear resistive elements. A low number of transistors are needed for each rule circuit, because the same devices cumulate several processing steps of the computation. Another property of the circuit is that the power consumed by a given rule is nearly zero when the weight of that rule is zero. This property enables an efficient use of power in integrated circuits containing fuzzy rule arrays, since normally only a few rules are active simultaneously. In addition, the proposed circuit features an analog center-of-gravity defuzzification circuit which can process digitally stored parameters without local D/A conversion. A completely functional research prototype with 80 rules was fabricated in a 2 /spl mu/m CMOS technology. The chip core area is 1.32 mm/sup 2/, the power consumption is 850 nW with a 1.8 V supply, and the 90% settling time in response to an input step is less than 400 /spl mu/s.