Sarmad Ozan, Manish Nair, Tommaso A. Cappello, M. Beach
{"title":"用于中频5G接收机的宽带前馈线性化低噪声放大器","authors":"Sarmad Ozan, Manish Nair, Tommaso A. Cappello, M. Beach","doi":"10.1109/APCCAS50809.2020.9301695","DOIUrl":null,"url":null,"abstract":"This paper proposes a wideband linearisation technique for third-order intercept point (IP3) improvement in low noise amplifiers (LNAs). The proposed LNA is designed for mid-band 5G (3-4GHz) wireless receivers and it is based on a cascode topology. An auxiliary transistor provides a feedforward correction path for third-order intermodulation (IM3) cancellation. The effects of the second harmonic on the IM3 are also considered in the modelling. Theoretical and simulation analysis of the circuit result in a DC power consumption of 306mW from a supply voltage of 3V, an OIP3 of 30.8dBm, noise figure (NF) of 0.94dB and 13.8dB of power gain are obtained. The LNA is simulated for a hybrid circuit implementation using a 400um GaAs packaged transistor.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Low-Noise Amplifier with Wideband Feedforward Linearisation for Mid-Band 5G Receivers\",\"authors\":\"Sarmad Ozan, Manish Nair, Tommaso A. Cappello, M. Beach\",\"doi\":\"10.1109/APCCAS50809.2020.9301695\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a wideband linearisation technique for third-order intercept point (IP3) improvement in low noise amplifiers (LNAs). The proposed LNA is designed for mid-band 5G (3-4GHz) wireless receivers and it is based on a cascode topology. An auxiliary transistor provides a feedforward correction path for third-order intermodulation (IM3) cancellation. The effects of the second harmonic on the IM3 are also considered in the modelling. Theoretical and simulation analysis of the circuit result in a DC power consumption of 306mW from a supply voltage of 3V, an OIP3 of 30.8dBm, noise figure (NF) of 0.94dB and 13.8dB of power gain are obtained. The LNA is simulated for a hybrid circuit implementation using a 400um GaAs packaged transistor.\",\"PeriodicalId\":127075,\"journal\":{\"name\":\"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\",\"volume\":\"77 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-12-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCCAS50809.2020.9301695\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS50809.2020.9301695","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Low-Noise Amplifier with Wideband Feedforward Linearisation for Mid-Band 5G Receivers
This paper proposes a wideband linearisation technique for third-order intercept point (IP3) improvement in low noise amplifiers (LNAs). The proposed LNA is designed for mid-band 5G (3-4GHz) wireless receivers and it is based on a cascode topology. An auxiliary transistor provides a feedforward correction path for third-order intermodulation (IM3) cancellation. The effects of the second harmonic on the IM3 are also considered in the modelling. Theoretical and simulation analysis of the circuit result in a DC power consumption of 306mW from a supply voltage of 3V, an OIP3 of 30.8dBm, noise figure (NF) of 0.94dB and 13.8dB of power gain are obtained. The LNA is simulated for a hybrid circuit implementation using a 400um GaAs packaged transistor.