Jahid Hasan Ridoy, Atik Yasir Rahman, Fahad Raihan Saquib
{"title":"基于D触发器的低功耗CNTFET的改进设计与比较","authors":"Jahid Hasan Ridoy, Atik Yasir Rahman, Fahad Raihan Saquib","doi":"10.1109/ECCE57851.2023.10101615","DOIUrl":null,"url":null,"abstract":"Carbon nanotube field effect transistors (CNTFETs) are auspicious nanoscale devices for realizing high performance with very thick and low power circuits. In this paper, different parameters of CNTFET from previous works have been studied and analyzed. Then, leakage current and leakage power of the proposed D flip-flop were compared with different reference circuits. The main goal is to improve, develop and design a CNTFET based D flip-flop. CNTFET's leakage current and leakage power consumption reduced drastically by decreasing diameter of CNT and number of CNT used in the CNTFET, which affected overall CNTFET's power consumption obviously. The proposed D flip-flop exhibited exquisite performance in case of leakage power consumption, having an average of 10.306 nW only, which is extremely low compared to the contemporary circuits. The chosen thickness of oxide and CNT's length for all the CNTFETs are 5 nm and 16 nm respectively. These CNTFETs are based on the results gathered from so that not only they can act as a D flip-flop correctly but also total power consumption of the device would be reduced as much as possible.","PeriodicalId":131537,"journal":{"name":"2023 International Conference on Electrical, Computer and Communication Engineering (ECCE)","volume":"52 3","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Improved Design and Comparison of a Low Power CNTFET based on D Flip-Flop\",\"authors\":\"Jahid Hasan Ridoy, Atik Yasir Rahman, Fahad Raihan Saquib\",\"doi\":\"10.1109/ECCE57851.2023.10101615\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Carbon nanotube field effect transistors (CNTFETs) are auspicious nanoscale devices for realizing high performance with very thick and low power circuits. In this paper, different parameters of CNTFET from previous works have been studied and analyzed. Then, leakage current and leakage power of the proposed D flip-flop were compared with different reference circuits. The main goal is to improve, develop and design a CNTFET based D flip-flop. CNTFET's leakage current and leakage power consumption reduced drastically by decreasing diameter of CNT and number of CNT used in the CNTFET, which affected overall CNTFET's power consumption obviously. The proposed D flip-flop exhibited exquisite performance in case of leakage power consumption, having an average of 10.306 nW only, which is extremely low compared to the contemporary circuits. The chosen thickness of oxide and CNT's length for all the CNTFETs are 5 nm and 16 nm respectively. These CNTFETs are based on the results gathered from so that not only they can act as a D flip-flop correctly but also total power consumption of the device would be reduced as much as possible.\",\"PeriodicalId\":131537,\"journal\":{\"name\":\"2023 International Conference on Electrical, Computer and Communication Engineering (ECCE)\",\"volume\":\"52 3\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-02-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 International Conference on Electrical, Computer and Communication Engineering (ECCE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECCE57851.2023.10101615\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 International Conference on Electrical, Computer and Communication Engineering (ECCE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECCE57851.2023.10101615","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Improved Design and Comparison of a Low Power CNTFET based on D Flip-Flop
Carbon nanotube field effect transistors (CNTFETs) are auspicious nanoscale devices for realizing high performance with very thick and low power circuits. In this paper, different parameters of CNTFET from previous works have been studied and analyzed. Then, leakage current and leakage power of the proposed D flip-flop were compared with different reference circuits. The main goal is to improve, develop and design a CNTFET based D flip-flop. CNTFET's leakage current and leakage power consumption reduced drastically by decreasing diameter of CNT and number of CNT used in the CNTFET, which affected overall CNTFET's power consumption obviously. The proposed D flip-flop exhibited exquisite performance in case of leakage power consumption, having an average of 10.306 nW only, which is extremely low compared to the contemporary circuits. The chosen thickness of oxide and CNT's length for all the CNTFETs are 5 nm and 16 nm respectively. These CNTFETs are based on the results gathered from so that not only they can act as a D flip-flop correctly but also total power consumption of the device would be reduced as much as possible.