{"title":"1.5 ppm/°C纳米瓦无电阻mos唯一电压参考","authors":"C. JhonA.Gomez, H. Klimach, E. Fabris, S. Bampi","doi":"10.1109/LASCAS.2016.7451019","DOIUrl":null,"url":null,"abstract":"This paper presents a MOS-only high power supply rejection (PSRR) voltage reference with a very low temperature coefficient (TC) that consumes only tens of nano-Watt. It is composed by a threshold voltage monitor circuit with no resistors, cascaded with a thermal voltage generator, adequate for fabrication in standard processes. Since the MOS transistors operate in subthreshold and near-threshold regimes the current consumption is very low. The operation of the circuit is analytically described and a design methodology is proposed. Post-layout simulations for a design in a 130 nm CMOS process are presented, resulting a reference voltage around 670 mV with a best case TC of 1.5 ppm/°C for the -40 to +125 °C range and an average TC of 20 ppm/°C over process variations, untrimmed. A very low sensitivity to VDD is achieved, resulting a PSRR lower than -71 dB at 100 Hz and a line sensitivity (LS) lower than 576 ppm/V for a supply range from 1 to 3 V. The area is very small, 0.0084 mm2 including the start-up stage.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"1.5 ppm/°C nano-Watt resistorless MOS-only voltage reference\",\"authors\":\"C. JhonA.Gomez, H. Klimach, E. Fabris, S. Bampi\",\"doi\":\"10.1109/LASCAS.2016.7451019\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a MOS-only high power supply rejection (PSRR) voltage reference with a very low temperature coefficient (TC) that consumes only tens of nano-Watt. It is composed by a threshold voltage monitor circuit with no resistors, cascaded with a thermal voltage generator, adequate for fabrication in standard processes. Since the MOS transistors operate in subthreshold and near-threshold regimes the current consumption is very low. The operation of the circuit is analytically described and a design methodology is proposed. Post-layout simulations for a design in a 130 nm CMOS process are presented, resulting a reference voltage around 670 mV with a best case TC of 1.5 ppm/°C for the -40 to +125 °C range and an average TC of 20 ppm/°C over process variations, untrimmed. A very low sensitivity to VDD is achieved, resulting a PSRR lower than -71 dB at 100 Hz and a line sensitivity (LS) lower than 576 ppm/V for a supply range from 1 to 3 V. The area is very small, 0.0084 mm2 including the start-up stage.\",\"PeriodicalId\":129875,\"journal\":{\"name\":\"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-04-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/LASCAS.2016.7451019\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LASCAS.2016.7451019","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
1.5 ppm/°C nano-Watt resistorless MOS-only voltage reference
This paper presents a MOS-only high power supply rejection (PSRR) voltage reference with a very low temperature coefficient (TC) that consumes only tens of nano-Watt. It is composed by a threshold voltage monitor circuit with no resistors, cascaded with a thermal voltage generator, adequate for fabrication in standard processes. Since the MOS transistors operate in subthreshold and near-threshold regimes the current consumption is very low. The operation of the circuit is analytically described and a design methodology is proposed. Post-layout simulations for a design in a 130 nm CMOS process are presented, resulting a reference voltage around 670 mV with a best case TC of 1.5 ppm/°C for the -40 to +125 °C range and an average TC of 20 ppm/°C over process variations, untrimmed. A very low sensitivity to VDD is achieved, resulting a PSRR lower than -71 dB at 100 Hz and a line sensitivity (LS) lower than 576 ppm/V for a supply range from 1 to 3 V. The area is very small, 0.0084 mm2 including the start-up stage.