基于模型的fpga硬件SC极解码器设计

Yann Delomier, B. Gal, J. Crenne, C. Jégo
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引用次数: 5

摘要

Polar码是一种新的纠错码族,与LDPC码和涡轮码相比,应该对其进行基准测试和评估。事实上,5G数字通信标准的最新进展建议在EMBB控制信道中使用极性编码。然而,在许多情况下,实现高效的FEC硬件解码器是具有挑战性的。需要专业知识来支持和促进测试、快速设计迭代和快速原型。在本文中,提出了一种基于模型的设计方法来生成高效的硬件SC极性码解码器。利用HLS设计流程和工具,我们演示了FPGA系统设计人员如何快速开发具有良好性能的复杂硬件系统。当使用相关的计算模型时,强调了设计空间探索对可实现性能的有利影响。对抽象层的灵活性进行了评估。对硬件解码器的生成效率进行了评估和比较。结果表明,计算并行度、位长度、剪枝水平和工作频率的微调有助于设计具有中等硬件复杂性的高吞吐量解码器。在Xilinx Virtex-7设备和Altera Stratix IV设备上实现了超过300 Mbps的解码吞吐量。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Model-based Design of Hardware SC Polar Decoders for FPGAs
Polar codes are a new error correction code family that should be benchmarked and evaluated in comparison to LDPC and turbo-codes. Indeed, recent advances in the 5G digital communication standard recommended the use of polar codes in EMBB control channels. However, in many cases, the implementation of efficient FEC hardware decoders is challenging. Specialised knowledge is required to enable and facilitate testing, rapid design iterations, and fast prototyping. In this article, a model-based design methodology to generate efficient hardware SC polar code decoders is presented. With HLS design process and tools, we demonstrate how FPGA system designers can quickly develop complex hardware systems with good performances. The favourable impact of design space exploration is underlined on achievable performances when a relevant computation model is used. The flexibility of the abstraction layers is evaluated. Hardware decoder generation efficiency is assessed and compared to competing approaches. It is shown that the fine-tuning of computation parallelism, bit length, pruning level, and working frequency help to design high-throughput decoders with moderate hardware complexities. Decoding throughputs higher than 300 Mbps are achieved on an Xilinx Virtex-7 device and on an Altera Stratix IV device.
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