{"title":"运载火箭中拜占庭弹性计算的系统架构","authors":"M. Iacoponi, R. Grisell","doi":"10.1109/DASC.1990.111307","DOIUrl":null,"url":null,"abstract":"A system architecture for fault-tolerant computation is presented that meets or exceeds projected unmanned and manned launch vehicle requirements. The system architecture discussed is under development at Harris Corporation on the Advanced Fault-Tolerant Data Processor (AFTDP) project. The AFTDP addresses both long-life missions where resource preservation is critical and shorter-life ultra-reliable missions relevant to launch vehicle applications. A distributed computation model is used to achieve robust fault tolerance based on a Byzantine fault model. The AFTDP employs a high-performance shared-memory multiprocessing model of computation for application programs, which is based on a 20 million instruction per second RISC (reduced-instruction-set computer) processor.<<ETX>>","PeriodicalId":141205,"journal":{"name":"9th IEEE/AIAA/NASA Conference on Digital Avionics Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"System architecture for Byzantine resilient computation in launch vehicle applications\",\"authors\":\"M. Iacoponi, R. Grisell\",\"doi\":\"10.1109/DASC.1990.111307\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A system architecture for fault-tolerant computation is presented that meets or exceeds projected unmanned and manned launch vehicle requirements. The system architecture discussed is under development at Harris Corporation on the Advanced Fault-Tolerant Data Processor (AFTDP) project. The AFTDP addresses both long-life missions where resource preservation is critical and shorter-life ultra-reliable missions relevant to launch vehicle applications. A distributed computation model is used to achieve robust fault tolerance based on a Byzantine fault model. The AFTDP employs a high-performance shared-memory multiprocessing model of computation for application programs, which is based on a 20 million instruction per second RISC (reduced-instruction-set computer) processor.<<ETX>>\",\"PeriodicalId\":141205,\"journal\":{\"name\":\"9th IEEE/AIAA/NASA Conference on Digital Avionics Systems\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-10-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"9th IEEE/AIAA/NASA Conference on Digital Avionics Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DASC.1990.111307\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"9th IEEE/AIAA/NASA Conference on Digital Avionics Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DASC.1990.111307","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
System architecture for Byzantine resilient computation in launch vehicle applications
A system architecture for fault-tolerant computation is presented that meets or exceeds projected unmanned and manned launch vehicle requirements. The system architecture discussed is under development at Harris Corporation on the Advanced Fault-Tolerant Data Processor (AFTDP) project. The AFTDP addresses both long-life missions where resource preservation is critical and shorter-life ultra-reliable missions relevant to launch vehicle applications. A distributed computation model is used to achieve robust fault tolerance based on a Byzantine fault model. The AFTDP employs a high-performance shared-memory multiprocessing model of computation for application programs, which is based on a 20 million instruction per second RISC (reduced-instruction-set computer) processor.<>
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