{"title":"集成电网建模与分析","authors":"Yong Wang, D. Quint, E. Fetzer","doi":"10.1109/EPEP.2003.1250060","DOIUrl":null,"url":null,"abstract":"This paper presents a new approach for the integrated power grid modeling and analysis. A loop-based inductance model is used to simplify the package and on-chip circuit model. A more accurate on-chip load model is created for current and future IC processes.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"82 1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Integrated power grid modeling and analysis\",\"authors\":\"Yong Wang, D. Quint, E. Fetzer\",\"doi\":\"10.1109/EPEP.2003.1250060\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a new approach for the integrated power grid modeling and analysis. A loop-based inductance model is used to simplify the package and on-chip circuit model. A more accurate on-chip load model is created for current and future IC processes.\",\"PeriodicalId\":254477,\"journal\":{\"name\":\"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)\",\"volume\":\"82 1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-12-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPEP.2003.1250060\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEP.2003.1250060","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents a new approach for the integrated power grid modeling and analysis. A loop-based inductance model is used to simplify the package and on-chip circuit model. A more accurate on-chip load model is created for current and future IC processes.
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