Time-to-Digital Converter with Pseudo-Segmented Delay Line

This paper presents a time-to-digital converter (TDC) with pseudo-segmented delay line implemented in 28 nm field-programmable gate array (FPGA) device (Kintex-7 XC7K160T, Xilinx). The TDC employs a carry chain based delay line wherein each tap is connected to multiple flip-flops. Proposed solution gives the same measurement resolution and comparable precision improvement as using multiple time coding lines (TCL) but allows to save logical resources available in FPGA chip. The TDC was tested in timestamps based time interval counter operating at 700 MHz clock and provides 1.1 ps resolution and 5 ps precision.