22纳米FDSOI CMOS毫米波噪声建模与分析

2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems Pub Date : 2023-01-22 DOI:10.1109/SiRF56960.2023.10046210

Q. H. Le, D. K. Huynh, S. Lehmann, Zhixing Zhao, C. Schwan, T. Kämpfe, M. Rudolph

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引用次数: 3

摘要

本文对22nm FDSOI CMOS工艺中的高频噪声进行了建模和分析。利用基于调谐器的方法提取了多指n通道晶体管高达170 GHz的实验噪声参数。应用Pucel (PRC)噪声模型对22 nm FDSOI低频到d波段的噪声特性进行了预测和验证。此外，还演示了模型参数与w频段漏极电流的提取和分析。

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22-nm FDSOI CMOS Noise Modeling and Analysis in mm-Wave Frequency Range

This paper presents the modeling and analysis of the high-frequency noise in 22-nm FDSOI CMOS technology. Experimental noise parameters up to 170 GHz of a multi-finger n-channel transistor are extracted by utilizing the tuner-based method. The Pucel (PRC) noise model is applied and validated for prediction of 22-nm FDSOI noise characteristics from low frequencies to D-band frequencies. In addition, extraction and analysis of the model parameters versus drain current at the W-band frequency 94 GHz are demonstrated.

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来源期刊

2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

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