LTSSM的VLSI实现

2017 International conference of Electronics, Communication and Aerospace Technology (ICECA) Pub Date : 2017-04-01 DOI:10.1109/ICECA.2017.8203658

R. T. N. Chappa, B. Jammu, Maheswari Adimulam, Maneesh Ayi

{"title":"LTSSM的VLSI实现","authors":"R. T. N. Chappa, B. Jammu, Maheswari Adimulam, Maneesh Ayi","doi":"10.1109/ICECA.2017.8203658","DOIUrl":null,"url":null,"abstract":"Link Training and Status State Machine (LTSSM) is a state machine in Universal Serial Bus (USB) which is defined for link connectivity and the link power management. LTSSM consists of 12 distinct states which are characterized depending on their functionalities. This paper reveals the FPGA implementation of LTSSM providing with USB 3.1 specifications with a support of USB 3.0 and 2.0 specifications also. The implementation includes the transition of all states present in the state machine. Further LTSSM has been designed by using Verilog code and simulated, synthesized and programmed to the targeted Artix-7 family of FPGA in the Vivado Xilinx environment.","PeriodicalId":222768,"journal":{"name":"2017 International conference of Electronics, Communication and Aerospace Technology (ICECA)","volume":"48 17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"VLSI implementation of LTSSM\",\"authors\":\"R. T. N. Chappa, B. Jammu, Maheswari Adimulam, Maneesh Ayi\",\"doi\":\"10.1109/ICECA.2017.8203658\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Link Training and Status State Machine (LTSSM) is a state machine in Universal Serial Bus (USB) which is defined for link connectivity and the link power management. LTSSM consists of 12 distinct states which are characterized depending on their functionalities. This paper reveals the FPGA implementation of LTSSM providing with USB 3.1 specifications with a support of USB 3.0 and 2.0 specifications also. The implementation includes the transition of all states present in the state machine. Further LTSSM has been designed by using Verilog code and simulated, synthesized and programmed to the targeted Artix-7 family of FPGA in the Vivado Xilinx environment.\",\"PeriodicalId\":222768,\"journal\":{\"name\":\"2017 International conference of Electronics, Communication and Aerospace Technology (ICECA)\",\"volume\":\"48 17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 International conference of Electronics, Communication and Aerospace Technology (ICECA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECA.2017.8203658\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International conference of Electronics, Communication and Aerospace Technology (ICECA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECA.2017.8203658","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

链路训练状态机(LTSSM)是通用串行总线(USB)上的一种状态机，用于链路连接和链路电源管理。LTSSM由12个不同的状态组成，这些状态的特征取决于它们的功能。本文介绍了LTSSM的FPGA实现，提供usb3.1规范，同时支持usb3.0和2.0规范。实现包括状态机中所有状态的转换。进一步的LTSSM已通过使用Verilog代码进行设计，并在Vivado Xilinx环境中对目标Artix-7系列FPGA进行模拟、合成和编程。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

VLSI implementation of LTSSM

Link Training and Status State Machine (LTSSM) is a state machine in Universal Serial Bus (USB) which is defined for link connectivity and the link power management. LTSSM consists of 12 distinct states which are characterized depending on their functionalities. This paper reveals the FPGA implementation of LTSSM providing with USB 3.1 specifications with a support of USB 3.0 and 2.0 specifications also. The implementation includes the transition of all states present in the state machine. Further LTSSM has been designed by using Verilog code and simulated, synthesized and programmed to the targeted Artix-7 family of FPGA in the Vivado Xilinx environment.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2017 International conference of Electronics, Communication and Aerospace Technology (ICECA)

自引率

0.00%

发文量