{"title":"紧耦合容错多处理器中的缓存管理","authors":"M. Banâtre, Philippe Joubert","doi":"10.1109/FTCS.1990.89339","DOIUrl":null,"url":null,"abstract":"Some aspects of a fault-tolerant tightly coupled multiprocessor architecture are presented. The originality of this architecture resides in the use of a stable transactional memory shared by all processors. To ensure fault tolerance, each update of a memory block is included into an atomic transaction managed by the stable transactional memory. All the blocks that are part of a transaction are written back atomically into stable transaction memory. This work focuses on a protocol which ensures the atomic update of blocks into stable transactional memory when they have been modified by several caches. The results of various simulations that were conducted in order to evaluate the potential performance of the proposed architecture are also presented.<<ETX>>","PeriodicalId":174189,"journal":{"name":"[1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"25","resultStr":"{\"title\":\"Cache management in a tightly coupled fault tolerant multiprocessor\",\"authors\":\"M. Banâtre, Philippe Joubert\",\"doi\":\"10.1109/FTCS.1990.89339\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Some aspects of a fault-tolerant tightly coupled multiprocessor architecture are presented. The originality of this architecture resides in the use of a stable transactional memory shared by all processors. To ensure fault tolerance, each update of a memory block is included into an atomic transaction managed by the stable transactional memory. All the blocks that are part of a transaction are written back atomically into stable transaction memory. This work focuses on a protocol which ensures the atomic update of blocks into stable transactional memory when they have been modified by several caches. The results of various simulations that were conducted in order to evaluate the potential performance of the proposed architecture are also presented.<<ETX>>\",\"PeriodicalId\":174189,\"journal\":{\"name\":\"[1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-06-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"25\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/FTCS.1990.89339\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FTCS.1990.89339","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Cache management in a tightly coupled fault tolerant multiprocessor
Some aspects of a fault-tolerant tightly coupled multiprocessor architecture are presented. The originality of this architecture resides in the use of a stable transactional memory shared by all processors. To ensure fault tolerance, each update of a memory block is included into an atomic transaction managed by the stable transactional memory. All the blocks that are part of a transaction are written back atomically into stable transaction memory. This work focuses on a protocol which ensures the atomic update of blocks into stable transactional memory when they have been modified by several caches. The results of various simulations that were conducted in order to evaluate the potential performance of the proposed architecture are also presented.<>