具有三维应变工程特点的工艺应变Si (PSS) CMOS技术

IEEE International Electron Devices Meeting 2003 Pub Date : 2003-12-08 DOI:10.1109/IEDM.2003.1269169

C. Ge, C.C. Lin, C. Ko, C.C. Huang, Y. Huang, B. Chan, B.-C. Perng, C. Sheu, Pang-Yen Tsai, L. Yao, C.-L. Wu, T. Lee, C. Chen, C. Wang, S.C. Lin, Y. Yeo, C. Hu

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引用次数: 106

摘要

我们报告了一个过程应变Si (PSS) CMOS技术的演示使用三维(3D)应变工程的概念。制备PSS的方法包括对沟槽隔离、硅化物和帽层进行应力工程，以同时提高NMOS和PMOS的性能。每种方法都能使环形振荡器(RO)的速度提高5-10%。利用一种或多种PSS技术的3D应变工程优势，可以进一步提高CMOS的性能。PSS是一种符合CMOS功率性能要求的低成本技术。

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Process-strained Si (PSS) CMOS technology featuring 3D strain engineering

We report the demonstration of a process-strained Si (PSS) CMOS technology using the concept of three-dimensional (3D) strain engineering. Methods of producing PSS include stress engineering of trench isolation, silicide, and cap layer, to improve NMOS and PMOS performance simultaneously. Each of these approaches results in a 5-10% enhancement in the ring oscillator (RO) speed. By taking advantage of preferential 3D strain engineering via one or combining more PSS techniques, CMOS performance can be further improved. PSS is a cost effective technology for meeting CMOS power-performance requirements.

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IEEE International Electron Devices Meeting 2003

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