A modified cascaded sigma-delta modulator with improved linearity

This paper presents a sigma-delta modulator architecture with improved linearity over a frequency band from DC to 10MHz. The proposed modulator architecture employs the 2nd order 4-bit sigma-delta modulator with feedforward signal path in a 2-2 modified cascaded configuration, which greatly improves the tonal behavior even at 8X oversampling ratio (OSR). A data-weighted-averaging technique eliminates tones generated by the multibit digital-to-analog converter (DAC) nonlinearity improving the spurious free dynamic range (SFDR) and intermodulation distortion performance. The modulator is designed in 0.18/spl mu/m CMOS process and operates at 1.8V supply voltage. It achieves 62.86 dB signal-to-noise plus distortion ratio (SNDR) in the 10MHz signal bandwidth, a SFDR of 82.2dB and IMD3 of -77.5dB.