FPGA based implementation of pulsed radar with time delay in digital beamforming using partially serial architecture

The Radars have been using the composition of digital and analog beamforming. In the analog beamforming at the output of phase shifters the sub-arrays are digitized. But such type of systems languishes with immured bandwidth and will not be capable to constitute concurrent beam. While in case of digital beamforming there are some assistance like broad bandwidth waveforms and concurrent beams at peculiar angles, frequencies and waveforms. These types of techniques were also costly in the previous years. But as per the presence of numerous multipliers in the field programmable gate arrays(FPGA) and converters it is in reach. In this paper, the implementation of fractional delay filter(FD) using partially serial architecture is done. It is further simulated with ISE using devices, SPARTAN-3ADSP and VIRTEX 5. In the end, the analogy of SPARTAN-3ADSP based XC3SD1800ACS484-4 device with VIRTEX 5 based XC5VLX50TFF1136-3 is shown. The result shows that the fractional delay filter on VIRTEX 5 is 128.94 times faster than SPARTAN-3ADSP.