A 1–21 GHz, 3-bit CMOS true time delay chain with 274 ps delay for ultra-broadband phased array antennas

A CMOS true time delay (TTD) chain operating from 1 GHz to 21 GHz is presented for ultra-broadband phased array systems. An eight-stage trombone configuration is employed to provide 3-bit tuning capability. The second order all pass network (APN) is used to construct the gate line and drain line. The adoption of the APN increases the achievable delay while maintaining a compact size. The larger shunt capacitance in the APN also helps to alleviate the design constraints for the switching amplifiers in the trombone topology. The all-pass characteristic of the APN further improves the matching performance of the trombone lines and hence extends the operating bandwidth. The circuit is implemented in a standard 0.13 μm CMOS process. The measured input and output return loss is better than 12 dB across 1-21 GHz and the maximum delay is 274 ps with 3-bit resolution. The measured input referred P1dB is better than -2.5 dBm.