A High Signal-Integrity PCB-Trace with Embedded Chip Capacitors and Its Design Methodology Using Genetic Algorithm

Signal integrity (SI) degradation in printed circuit boards (PCBs) has been becoming more serious problem in GHz domain due to the difficulty of impedance matching designs. In this paper, we propose a novel trace structure called capacitor- segmental transmission line (C-STL) and its design methodology to overcome the SI degradation problem. In the C-STL, we intentionally generate reflection waves, or noises due to impedance mismatching by embedded chip capacitors connected to the trace, or transmission line in the PCB, and superpose the reflection waves onto the distorted digital signals to shape it to ideal ones. We use genetic algorithm to design the C-STL because chip-capacitor-selection becomes a combinatorial explosion problem. We fabricate a C-STL prototype and demonstrate its high SI improvement capability by eye-diagram measurements.