{"title":"在宽频率范围内具有高PSR的无电容LDO","authors":"Iulian Sularea, C. Răducan, M. Neag","doi":"10.1109/CAS52836.2021.9604164","DOIUrl":null,"url":null,"abstract":"This paper presents a capacitor-less low dropout (LDO) voltage PMOS regulator with high power supply rejection (PSR). The proposed LDO combines into a single core two differential stages: a primary one - as error amplifier for the negative feedback loop - and a secondary one, used to create a feedforward cancellation path from the supply to the gate of the pass transistor. With this arrangement the LDO can provide a PSR of -43dB at 1MHz for the maximum load current of 50mA. This performance is achieved with only 20µA quiescent current and a load capacitor of 100pF. The LDO is designed in a 0.18µm standard CMOS process.","PeriodicalId":281480,"journal":{"name":"2021 International Semiconductor Conference (CAS)","volume":"16 9-12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A Capacitor-less LDO with High PSR over a wide frequency range\",\"authors\":\"Iulian Sularea, C. Răducan, M. Neag\",\"doi\":\"10.1109/CAS52836.2021.9604164\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a capacitor-less low dropout (LDO) voltage PMOS regulator with high power supply rejection (PSR). The proposed LDO combines into a single core two differential stages: a primary one - as error amplifier for the negative feedback loop - and a secondary one, used to create a feedforward cancellation path from the supply to the gate of the pass transistor. With this arrangement the LDO can provide a PSR of -43dB at 1MHz for the maximum load current of 50mA. This performance is achieved with only 20µA quiescent current and a load capacitor of 100pF. The LDO is designed in a 0.18µm standard CMOS process.\",\"PeriodicalId\":281480,\"journal\":{\"name\":\"2021 International Semiconductor Conference (CAS)\",\"volume\":\"16 9-12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-10-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 International Semiconductor Conference (CAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CAS52836.2021.9604164\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 International Semiconductor Conference (CAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CAS52836.2021.9604164","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Capacitor-less LDO with High PSR over a wide frequency range
This paper presents a capacitor-less low dropout (LDO) voltage PMOS regulator with high power supply rejection (PSR). The proposed LDO combines into a single core two differential stages: a primary one - as error amplifier for the negative feedback loop - and a secondary one, used to create a feedforward cancellation path from the supply to the gate of the pass transistor. With this arrangement the LDO can provide a PSR of -43dB at 1MHz for the maximum load current of 50mA. This performance is achieved with only 20µA quiescent current and a load capacitor of 100pF. The LDO is designed in a 0.18µm standard CMOS process.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
