Parallel placement of parallel processes

The problem of placing the individual processes of a logically partitioned problem on the nodes of a multiprocessor in such a manner as to minimize the communication and memory utilization costs is known as the process placement problem. This problem is, in general, NP-complete. A number of algorithms for finding approximate solutions to the process placement problem have been investigated. Some of these algorithms rely on heuristics to initially place the processes. This approach is sometimes followed by iterative refinement, where pairs of processes are swapped in a search for better approximations. For other algorithms which rely almost solely on iterative refinement, initial placement is of much less importance. Recently simulated annealing, a more sophisticated adaptive search technique, has been applied to the process placement problem. All of these process placement algorithms are sequential. (Although simulated annealing has recently been implemented in parallel on a hypercube architecture, no work has been done in applying the parallel version to the process placement problem.) The purpose of this paper is to discuss work with a parallel algorithm for approximating solutions to the process placement problem. The algorithm has been implemented on an Intel iPSC hypercube with 16 nodes. The class of problems which were investigated involve mapping logical problem graphs to physical architectural interconnection graphs (e.g., mapping a binary tree to a hypercube or mapping a hypercube to a hypercube). The algorithm (PGA) is a parallel version of genetic algorithms, an adaptive search technique based on the principles of population genetics. Unlike the previously mentioned algorithms, PGA can be implemented on the multiprocessor system to which the actual logical problem will be mapped.