IBM zSeries eServer z900系统的功能验证

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 2002-09-16 DOI:10.1109/ICCD.2002.1106741

Joerg Walter

{"title":"IBM zSeries eServer z900系统的功能验证","authors":"Joerg Walter","doi":"10.1109/ICCD.2002.1106741","DOIUrl":null,"url":null,"abstract":"This paper presents an overview on how the zSeries eServer z900 system has been functionally verified. It describes the hierarchical structure of verification, starting with designer simulation, unit-simulation, chip-simulation up to system simulation. For each step, the tools, methods and goals of verification are described. It also presents a description of the IT environment used at the different levels of verification, especially of dedicated simulation hardware like accelerator and emulator machines used for system simulation and hardware/software co-verification.","PeriodicalId":164768,"journal":{"name":"Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Functional verification of the IBM zSeries eServer z900 system\",\"authors\":\"Joerg Walter\",\"doi\":\"10.1109/ICCD.2002.1106741\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an overview on how the zSeries eServer z900 system has been functionally verified. It describes the hierarchical structure of verification, starting with designer simulation, unit-simulation, chip-simulation up to system simulation. For each step, the tools, methods and goals of verification are described. It also presents a description of the IT environment used at the different levels of verification, especially of dedicated simulation hardware like accelerator and emulator machines used for system simulation and hardware/software co-verification.\",\"PeriodicalId\":164768,\"journal\":{\"name\":\"Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-09-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCD.2002.1106741\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.2002.1106741","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

本文概述了如何对zSeries eServer z900系统进行功能验证。它描述了验证的层次结构，从设计者仿真、单元仿真、芯片仿真到系统仿真。对于每一步，都描述了验证的工具、方法和目标。它还描述了在不同验证级别上使用的It环境，特别是用于系统仿真和硬件/软件协同验证的专用仿真硬件，如加速器和仿真机。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Functional verification of the IBM zSeries eServer z900 system

This paper presents an overview on how the zSeries eServer z900 system has been functionally verified. It describes the hierarchical structure of verification, starting with designer simulation, unit-simulation, chip-simulation up to system simulation. For each step, the tools, methods and goals of verification are described. It also presents a description of the IT environment used at the different levels of verification, especially of dedicated simulation hardware like accelerator and emulator machines used for system simulation and hardware/software co-verification.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors

CiteScore

2.30

自引率

0.00%

发文量