I. Mendoza, José Luis Pizano Escalante, Joaquín Cortez González, Omar Humberto Longoria Gándara
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引用次数: 1
摘要
本文给出了一种双合并排序网络的实现结果。这用于MIMO空间调制(SM)通信的检测算法,并在英特尔Altera Cyclone IV FPGA上实现。这个排序网络有一个额外的特点,它指示要排序的数字的索引或入口顺序;即,排序向量的每个元素都有一定数量的位连接,表示它们的原始位置。此外,由于它是完全组合的,排序所花费的时间只是固有的传播延迟,即使不适合对大量元素进行排序,也具有很好的性能。根据要排序的元素数量和用于表示这些元素的位来实现完全参数化的排序网络是可能的,并且用于索引表示的资源使用与目前的实现相当。
Implementation of a parameterizable sorting network for spatial modulation detection on FPGA
In this paper, implementation results of a bitonic-merge sorting network are presented. This is used on a detection algorithm for MIMO Spatial Modulation (SM) communications and it is implemented on an Intel Altera Cyclone IV FPGA. This sorting network has the added peculiarity that it indicates the index or entrance order of the numbers to sort; i.e., each element of the sorted vector has a certain amount of bits concatenated indicative of their original position. Also, as it is completely combinational, the amount of time taken to sort is only the inherent propagation delay, having great performance even if it is not suitable to sort a great quantity of elements. It is possible to implement an entirely parametric sorting network in terms of the number of elements to sort and the bits used for representation of these elements, and the use of resources for index representation is comparable to present implementations.