Introduction to the new Packet Triggered Architecture for pipelined and parallel data processing

This paper describes a novel Packet Triggered Architecture (PTA). This architecture takes advantage of programmable pipeline and parallel processing, which lead to MIMD (Multiple Instruction Multiple Data) architecture. The PTA is composed of two main blocks. The first block is constituted from Functional Units (FUs) and their interconnection network. The instructions in the PTA are composed of instruction packets. Every packet encapsulates a data and route across internal NoC (Network on Chip) to which enables dynamic data flow scheduling. This approach brings a new way of programming, because the programming is done by specifying FUs addresses and functions ports. Using of such a design allows create target hardware like a software application. The main advantages of this approach are that any processor can be emulated in the PTA, its ISA can be extended and special accelerators can be added too. Small loops are created directly inside the PTA and small concurrent Finite State Automats (FSM) can be created inside the PTA. The PTA can be as well used like an abstraction layer to easily design and create special-purpose hardware. There are some advantages in hardware design as well. The PTA does not need any complex instruction decoder. Instructions packets can be only fetched and dispatched to PTA. The PTA as well does not need any complex forwarding logic. The PTA can work as a system with improved reliability as well.