Operation in Partitioned Circuits with Scalable Hardware Mechanism

We propose the Scalable Hardware Mechanism, which enables the operation of a partitioned circuit to prevent the degradation of clock frequency by minimizing its dependence on the usage and the type of FPGA. Our mechanism provides a reduced delay by the collective signal transmission with the partitioned AES code generation circuit and the character string edit distance calculation circuit as partitioned circuits. The collective signal transmission has attained 1.27 times improvement in the speed for the AES code generation circuit and 3.16 times improvement for the character string edit distance calculation circuit compared with the circuit by the conventional method.