时钟优化技术

Ang Boon Chong, Tan Say Hong, Koh Jid Ian, Mohamad Halim Izzat, Loo Gin Hao, Chin Kevin Che Chau
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引用次数: 2

摘要

在集成电路的设计收敛中,时钟树的合成是关键阶段之一。良好的时钟树合成质量将确保在路由后阶段更容易进行时序收敛。在设计融合阶段,用户可能需要多次重新旋转放置优化,时钟树优化,然后再进行具有良好定时质量的post路由优化,以获得高性能块。这个过程可能会消耗50%的后端设计周期,以确保一个体面的周转时间和可接受的后路线优化时序结果,然后再进行时序工程变更订单(ECO)。本文的目的是分享时钟树优化技术和优化技术的结果,从时序,功率和倾斜三个方面。希望这一发现能对时钟优化解决方案的设计界有所帮助。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Clock Optimization Techniques
In the ASIC design convergence, the clock tree synthesis is one of the critical phase. A good quality of clock tree synthesis will ensure easier timing convergence during post route phase. During design convergence phase, users may need to have multiple re-spins on placement optimization, clock tree optimization before proceeding to post route optimization with decent timing quality, for high performance blocks. This process may consume 50% of backend design cycle, to ensure a decent turn around time and acceptable timing results from post route optimization, before proceeding to timing engineering change order (ECO). The objective of this paper, is to share the clock tree optimization techniques and the result of the optimization techniques, from timing, power and skew aspects. Hopefully, the finding will benefit the design community in clock optimization solutions.
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