{"title":"超深亚微米CMOS级联电流反射镜OTA设计","authors":"E. Manolov","doi":"10.1109/ET.2017.8124365","DOIUrl":null,"url":null,"abstract":"The paper proposes a sizing procedure for design of cascode current mirror OTA in 45nm CMOS ultra-deep submicron technology. To this aim the basic relations in the discussed circuit are presented and a short characterization of the 45nm CMOS technology is made. The main considerations for the design of the circuit in subthreshold region of operation of transistors are pointed out and a semi-empirical sizing procedure is developed. It is applied in the design of three variants of the studied cascode current mirror OTA. The results from the simulations confirm the effectiveness of the proposed sizing procedure.","PeriodicalId":127983,"journal":{"name":"2017 XXVI International Scientific Conference Electronics (ET)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Design of cascode current mirror OTA in ultra-deep submicron CMOS technology\",\"authors\":\"E. Manolov\",\"doi\":\"10.1109/ET.2017.8124365\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper proposes a sizing procedure for design of cascode current mirror OTA in 45nm CMOS ultra-deep submicron technology. To this aim the basic relations in the discussed circuit are presented and a short characterization of the 45nm CMOS technology is made. The main considerations for the design of the circuit in subthreshold region of operation of transistors are pointed out and a semi-empirical sizing procedure is developed. It is applied in the design of three variants of the studied cascode current mirror OTA. The results from the simulations confirm the effectiveness of the proposed sizing procedure.\",\"PeriodicalId\":127983,\"journal\":{\"name\":\"2017 XXVI International Scientific Conference Electronics (ET)\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 XXVI International Scientific Conference Electronics (ET)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ET.2017.8124365\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 XXVI International Scientific Conference Electronics (ET)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ET.2017.8124365","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of cascode current mirror OTA in ultra-deep submicron CMOS technology
The paper proposes a sizing procedure for design of cascode current mirror OTA in 45nm CMOS ultra-deep submicron technology. To this aim the basic relations in the discussed circuit are presented and a short characterization of the 45nm CMOS technology is made. The main considerations for the design of the circuit in subthreshold region of operation of transistors are pointed out and a semi-empirical sizing procedure is developed. It is applied in the design of three variants of the studied cascode current mirror OTA. The results from the simulations confirm the effectiveness of the proposed sizing procedure.
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