Design of asynchronous registers for multimode baseband signals processing

A new design technology of multimode terminal allows a single device to take care any kind of data with different baseband signal formats and sample rates. The different signal formats and sample rates might be handled in radio frequency block or digital baseband block. This paper presents a design of asynchronous register in order to handle some different sample rates in the multimode terminal. The scheme take cares the multi-sample-rate data inputs come from five types of standard i.e. GSM, UMTS, WLAN, WiMAX, and LTE. The proposed system employs 30.72MHz sampling rate for the common clock. Moreover, the proposed system has been successfully verified on FPGA Xilinx Virtex 5.