Analysis of results obtained with a new proposed low area low power high speed fixed point adder

Integer addition is one of the most important operations in digital computers digital signal processing and. In fact the speed of adders affects the speed and performance of their processors. In digital signal processing, multiply and accumulate (MAC) unit plays an important role when designing digital filters. However, this role is doubled when multiplierless techniques such as distributed arithmetic (DA) are applied. In such techniques, the addition operation is the main scale when specifying some of the design parameters such as operation speed, design area, and the power consumed. This paper discusses the results obtained from the design analyzer for the proposed addition circuit together with the results obtained for the two most common adders i.e. the carry lookahead adder (CLA) and the ripple carry adder (RCA). The results obtained for the three different adders show that the proposed addition circuit has lowest area, lowest power consumption. On the other hand, the proposed adder has an operation speed higher than the RCA and a very close to the speed of the CLA. it is worth to mention here that the proposed design is based on the concept of applying a set of if-then rules. This set of rules calculates the out sum and carry in human-like way of processing.