P. Upadhyaya, J. Savoj, F. An, Ade Bekele, A. Jose, Bruce Xu, Zhaoyin Daniel Wu, D. Turker, H. A. Aslanzadeh, H. Hedayati, J. Im, Siok-Wei Lim, S. Chen, Toan Pham, Y. Frans, Ken Chang
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3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS
The introduction of high-speed backplane transceivers inside FPGAs has addressed critical issues such as the ease in scalability of performance, high availability, flexible architectures, the use of standards, and rapid time to market. These have been crucial to address the ever-increasing demand for bandwidth in communication and storage systems [1-3], requiring novel techniques in receiver (RX) and clocking circuits.
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