面向视觉计算的嵌入式FPGA操作系统(仅摘要)

Zhilei Chai, Jin Yu, Zhibin Wang, Jie Zhang, Haojie Zhou
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引用次数: 3

摘要

尽管FPGA的功耗和性能优势得到了广泛认可,但在基于FPGA的系统上设计应用程序传统上是硬件专家承担的任务。使具有较少系统级知识但具有较多算法知识的应用级编程人员能够方便地在fpga上实现其应用程序具有重要意义。为了方便应用级编程人员使用FPGA,本文提出了一种嵌入式FPGA操作系统。首先,构建特定的I/ o,优化FPGA内I/ o、DDR内存、用户ip等之间的总线互连,实现视觉计算;其次,对FPGA的I/ o、DDR内存、通信等资源进行管理,将用户从底层细节中解放出来。第三,在运行时动态调度FPGA上执行的任务(ip),使FPGA在必要时实现多路复用。通过将FPGA操作系统移植到不同的FPGA平台上,并在此基础上实现视觉算法,表明FPGA操作系统能够简化FPGA平台上的算法开发,提高用户应用的可移植性。此外,几种流行的视觉算法的实现结果表明,FPGA操作系统在视觉计算方面是高效的。最后,实验结果表明,对于需要更多FPGA资源的多种算法,在考虑FPGA SoC的情况下,多IP运行时任务调度比固定IP运行时任务调度更有效。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An Embedded FPGA Operating System Optimized for Vision Computing (Abstract Only)
Although FPGA's power and performance advantages were recognized widely, designing applications on FPGA-based systems is traditionally a task undertaken by hardware experts. It is significant to allow application-level programmers with less system-level but more algorithm knowledge to realize their applications conveniently on FPGAs. In this paper, an embedded FPGA operating system is proposed to facilitate application-level programmers to use FPGAs. Firstly, it builds specific I/Os and optimizes bus interconnection among I/Os, DDR memory, user IPs etc within the FPGA for vision computing. Secondly, it manages resources of the FPGA such as I/Os, DDR memory, communication etc, frees users from low-level details. Thirdly, it schedules tasks (IPs) executed on the FPGA dynamically in runtime, which makes the FPGA multiplexed when necessary. After porting the FPGA operating system to different FPGA platforms and implementing vision algorithms based on that, it shows the FPGA operating system is able to simplify algorithm development on FPGA platforms and improve portability of user applications. Furthermore, implementation results of several popular vision algorithms show the FPGA operating system is efficient and effective for vision computing. Finally, experimental results shows that for multiple algorithms requiring more FPGA resources, runtime task scheduling of multiple IPs is more efficient than a fixed IP when the SoC of FPGA is considered.
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