Design and Experimental Verification of a Single-Phase Asymmetric Hybrid Multi-level Inverter

In recent years, multi-level inverters have emerged as a feasible power conversion solution for medium and high power applications due to better harmonic performance and ability to operate at high voltage/power when compared to traditional two-level inverters. Since the output level of the multi-level inverters depends on the number of the switching elements, as more levels are required, more switching elements are used. This situation makes the circuit and the control design complex and the losses to upsurge. To overcome these limitations and produce low harmonic content at the output, reduced switch count topologies are popular. In this study, a single-phase asymmetric hybrid multi-level inverter is proposed by combining diode clamped and cascaded H-bridge topologies. The inputs of the proposed inverter are selected as two unequal DC voltage sources. In this regard, fewer switching elements are used to obtain the same number of voltage levels at the output when compared to traditional multi-level inverters. The efficiency and the harmonic performance of the proposed topology is both verified by simulation and experimental studies. The gating signals of the semiconductor switches are produced by phase disposition pulse width modulation with carriers’ frequency of 4 kHz. It is shown by the experiments that a maximum efficiency of 94 % and a total harmonic distortion of 29 % are attained in the case studies.