费米实验室加速器科学技术设施的机器保护系统

Jinyuan Wu, A. Warner, Ning Liu, R. Neswold, L. Carmichael
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引用次数: 1

摘要

费米实验室加速器科学技术设施(FAST)的机器保护系统(MPS)已经实施和测试。该系统接收来自多个子系统和设备的信号,这些信号传达了安全操作加速器所需的相关状态。逻辑决策是基于这些输入和一些预定义的用户设置,这些设置反过来控制光注入器激光器的门信号。该系统的输入有各种各样的信号类型、编码方法和紧急情况,该系统被设计以适应。MPS接收由束流损耗系统产生的快速关闭(FSD)信号,当沿着加速器束流线的几个地方的束流损耗高于可接受值时,MPS抑制束流或降低宏脉冲内的束流强度。TTL或继电器触点信号从真空系统,环面,磁铁系统等,选择极性,以确保安全运行的加速器意外事件,如电缆断开在实验大厅的恶劣工业环境。RS422串行通信方案用于操作许可产生模块和大量可移动设备之间的接口,每个设备报告多比特状态。该系统还支持在用户定义的较低波束水平下进行系统调试。该机器保护系统由两个市售的现成的基于VMEbus的模块和板载FPGA器件实现。该系统由单板CPU通过VMEbus进行监控。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
The machine protection system for the Fermilab Accelerator Science and Technology Facility
The Machine Protection System (MPS) for the Fermilab Accelerator Science and Technology Facility (FAST) has been implemented and tested. The system receives signals from several subsystems and devices which conveys the relevant status needed to the safely operate the accelerator. Logic decisions are made based on these inputs and some predefined user settings which in turn controls the gate signal to the laser of the photo injector. The inputs of the system have a wide variety of signal types, encoding methods and urgencies for which the system is designed to accommodate. The MPS receives fast shutdown (FSD) signals generated by the beam loss system and inhibits the beam or reduces the beam intensity within a macro-pulse when the beam losses at several places along the accelerator beam line are higher than acceptable values. TTL or relay contact signals from the vacuum system, toroids, magnet systems etc., are chosen with polarities that ensure safe operation of the accelerator from unintended events such as cable disconnection in the harsh industrial environment of the experimental hall. A RS422 serial communication scheme is used to interface the operation permit generator module and a large number of movable devices each reporting multi-bit status. The system also supports operations at user defined lower beam levels for system commissioning. The machine protection system is implemented with two commercially available off-the-shelf VMEbus based modules with on board FPGA devices. The system is monitored and controlled via the VMEbus by a single board CPU.
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