一种高效的带混合泵浦电路的1.5 V dram反偏置发生器

Symposium 1993 on VLSI Circuits Pub Date : 1993-05-19 DOI:10.1109/VLSIC.1993.920549

Y. Tsukikawa, T. Kajimoto, Yasuhiko Okasaka, Y. Morooka, K. Furutani, H. Miyamoto, H. Ozaki

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引用次数: 32

摘要

作者提出了一种新型混合泵浦电路(HPC)的高效反偏压(Vbb)发生器。该混合系统使用一个NMOS泵浦晶体管和一个PMOS泵浦晶体管，可以泵浦低至-Vcc水平而没有Vth损耗。通过在抽运电路区域采用三阱结构，NMOS晶体管可以作为不需要注入少数载流子的抽运晶体管使用。

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An efficient back-bias generator with hybrid pumping circuit for 1.5 V DRAMs

The authors propose an efficient back-bias voltage (Vbb) generator with a newly introduced hybrid pumping circuit (HPC). This hybrid system uses one NMOS pumping transistor and one PMOS pumping transistor and can pump as low as the -Vcc level without a Vth loss. By adopting a triple-well structure at the pumping circuit area, the NMOS transistor can be employed as a pumping transistor without minority carrier injection.

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Symposium 1993 on VLSI Circuits

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