用于QAM数字无线电调制解调器的2/spl mu/m Cmos数字自适应均衡器芯片

1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers Pub Date : 1988-10-01 DOI:10.1109/ISSCC.1988.663625

S. Meier, E. DeMan, T. Noll, U. Loibl, H. Klar

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引用次数: 18

摘要

报道了一种用于正交调幅数字无线电调制解调器的全数字自适应均衡器芯片的设计与制作。该芯片在94.6 mm/sup /的硅面积上包含107936个晶体管。该芯片采用2 μ m CMOS技术设计，时钟和采样率为23.5 MHz。因此，每个芯片面积的功能吞吐率为6.7 10/sup 11/等于闸赫兹/厘米/sup 2/。芯片的输入和输出是ECL兼容的，使用一个控制单元补偿晶体管参数变化的影响。为了保证不同工艺参数芯片之间的通信正常，提出了一种匹配的同步时钟方案。用4个芯片实现了一个复值均衡器，并在一个运行于35mhz时钟频率的16-QAM数字无线电调制解调器中进行了测试。>

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A 2/spl mu/m Cmos Digital Adaptive Equalizer Chip For QAM Digital Radio Modems

The design and fabrication of a fully digital adaptive equalizer chip for QAM (quadrature amplitude modulation) digital radio modems is reported. The chip contains 107936 transistors on a silicon area of 94.6 mm/sup 2/. The chip was designed in a 2- mu m CMOS technology for a clock and sampling rate of 23.5 MHz. Accordingly, the functional throughput rate per chip area is 6.7 10/sup 11/ eq. gates Hz/cm/sup 2/. The inputs and outputs of the chip are ECL compatible, using a control unit compensating the influence of transistor parameter variations. For proper communication between chips having different technology parameters, a matched clocking scheme for synchronization was developed. A complex-valued equalizer was realized with four chips and tested in a 16-QAM digital radio modem, running at 35-MHz clock frequency. >

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来源期刊

1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers

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